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All 4 Verilog 2 SystemVerilog 1 VHDL 1

Pranav-2045 / CORDIC

Star 4

Synthesizable 16-bit, 16-stage pipelined CORDIC engine in Verilog (Q2.14 fixed-point) computing high-throughput sine and cosine without hardware multipliers. Features valid_in/valid_out handshaking and self-checking verification.

fpga rtl verilog finite-state-machine icarus-verilog hardware-acceleration verilog-hdl xilinx-vivado cordic digital-logic-design pipelined cordic-algorithm synthesizable fixed-point-arithmetic gtk-wave test-bench-verification synthesizable-verilog verilog-2001 digital-verification
  • Updated Mar 24, 2026
  • Verilog

Pranav-2045 / riscv-5stage-pipelined-matmul

Star 3

Synthesizable 5-stage pipelined RV32I processor in Verilog featuring full hazard handling (forwarding, load-use stalls, branch flushes) and an integrated 64-cycle 4×4 matrix multiplication coprocessor.

python matrix-multiplication verilog computer-architecture icarus-verilog hardware-acceleration instruction-set-architecture rv32i processor-design forwarding-unit custom-assembler pipelined-processor risk-v risc-v-processor 32-bit-processor gtk-wave verilog-2001 hazard-handling
  • Updated Sep 21, 2026
  • Verilog

HarinandanAM / FPGA

Star 0

This repository showcases various projects developed on the DE10-Lite board (Intel MAX 10 FPGA) using Quartus Prime Lite software. Each project includes HDL code, testbenches, simulations, and pin assignments, providing a comprehensive view of the FPGA design process.

fsm fpga microcontrollers dsp vhdl verification uart testbenches verilog-hdl digital-circuits quartus pin-assignment qsf communication-protocols rtl-simulations gtk-wave ip-cores
  • Updated Sep 6, 2024
  • VHDL

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