physical-verification

Design-rule check: a GDS layout + a rule deck in, geometry violations out.

Layout Versus Schematic verification engine for semiconductor design flows

Autonomous agentic system for chip physical verification. Turns a natural language design rule spec into an executable KLayout DRC script, runs it against a GDSII layout, and self-corrects violations with bounded, re-verified repair attempts. Built on open EDA tooling, no proprietary PDK required.

Python-based FEOL DRC engine for configurable semiconductor layout verification using KLayout and YAML.

Python-based EDA automation framework for physical IP workflows, with automated tool orchestration, parallel PVT regression, custom-cell SPICE validation, structured result parsing, and engineering run dashboards.

AI-assisted triage of DRC reports on the open-source SKY130 PDK (KLayout + RAG + GLM)

This repo consists of Guest OS installation , usage and physical desgin and verification of a CMOS Inverter using open-pdk SKY WATER 130. Design includes usage of tools like Xschem ,Magic, NGspice and Netgen LVS

"10-day VSD Physical Verification workshop using the SKY130 open-source PDK and EDA tools".

Automated SKY130 DRC flow using KLayout, Python, and TCL to run custom design-rule checks, parse XML results, and generate an HTML violation dashboard.

Full-custom 8-bit pipelined Vedic multiplier in 90nm CMOS with hierarchical schematic/layout design, DRC/LVS-clean verification, post-layout simulation, and 50 MHz pipelined operation.