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pipelined-processor-design

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YaronH08 / FPGA-Based-Pipelined-MIPS-MCU-System

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This repository features the design and FPGA implementation of a complete MCU-style digital system built around a pipelined MIPS processor core. Features a multi-stage pipeline for maximized instruction throughput, complete with integration wrapper modules and system-level components optimized for hardware deployment.

pipelined-processor-design rtl-hardware-implementation fpga-based-digital-system-design system-level-digital-design modular-hardware-integration
  • Updated May 21, 2026
  • VHDL

abdulrahman-hussieni / 32Bit-MIPS-processor

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MIPS Processor Implementations (VHDL) | This repository contains multiple implementations of the MIPS (Microprocessor without Interlocked Pipelined Stages) architecture using VHDL. The project is designed for educational and academic purposes, helping students understand CPU architecture and datapath/control design. It includes Single-Cy

mips vhdl computer-organization hardware-design multi-cycle-cpu single-cycle-cpu pipelined-processor-design
  • Updated Dec 18, 2025
  • VHDL

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