Use an explicit FXC lane for hosted Windows software rendering

[proggeramlug]

Hosted Windows shared tests terminate with 0xc0000005 before reaching goldens. Local WARP controls reproduce the failure, and a debugger stack identifies the DXIL compute-shader optimizer during virtual-geometry traversal. All ten hierarchy tests pass serially with DXC, while both four-thread DXC controls crash; FXC passes the hierarchy group and complete library controls at four and eight threads.

Select DX12/FXC explicitly for the hosted Windows shared lane. Make the remaining ordinary GPU test helpers honor backend and compiler environment options, matching the existing visibility, virtual-geometry and golden helpers. Preserve adapter selection, capability requirements, assertions, thresholds, ignored tests and the ray-query helper's deliberate DXC requirement. The Windows engine's compiler policy is unchanged.

The candidate library suite passes with four threads and explicit FXC (489 passed, one ignored). Complete local shared runs pass under physical DX12/DXC and Vulkan, including all 93 goldens and remaining integration checks. Formatting, strict Clippy, repository contracts and diff checks pass. Committed Rust/workflow changes exactly match the tested candidate. Hosted Tests run 34552411807 passes all 22 jobs, including the Windows shared library stage (489 passed, one ignored), the real native build and all 20 example links. Hosted Windows goldens skip the CPU adapter; their nominal 93 "ok" results are not physical-image qualification. Local Radeon and hosted Metal checks provide the physical rendering evidence. Named full-hardware quality jobs remain skipped.

The expanded physical Radeon FXC run fails four layered-material goldens during pipeline compilation: implicit LUT derivatives make FXC attempt to unroll varying light loops (X3570/X3511). The shader and failing test definitions are byte-identical to #163; those failures are retained and a separate explicit-LOD correction is being tested. This PR does not claim full physical FXC qualification. See the diagnostic report.

Stacked on #163; advances #140. This is a software-renderer CI workaround, and the underlying WARP/DXIL access violation remains open. Physical DX12/DXC and wider platform/hardware acceptance remain separate requirements. #163's published camera-history evidence retains the original hosted failure.

Published report and evidence retain the WARP/DXIL crashes, debugger stack, FXC controls, separate physical-FXC failures and exact hosted/source receipts. ZIP SHA-256: 0c181559edb073296bd74367c865f457b067bdfafc0436dbda48c25b32adf407.

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