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TileOP: per-dimension static/dynamic B.DIM lowering (SS/SD/DS/DD) - #82

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VV0003 merged 3 commits into
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codex/per-dim-bdim-lowering
Sep 7, 2026
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TileOP: per-dimension static/dynamic B.DIM lowering (SS/SD/DS/DD)#82
VV0003 merged 3 commits into
linxfrom
codex/per-dim-bdim-lowering

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@VV0003 VV0003 commented Sep 7, 2026

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Summary

Split every lb0/lb1 B.DIM site in template_asm.hpp into four if constexpr branches on ValidCol/ValidRow:

  • static dimB.DIM zero, %c[imm] (assembler compresses to C.B.DIMI)
  • dynamic dimB.DIM %[reg], 0
  • lb2 always stays the immediate form (only TPREFETCH's dynamic-GM fallback keeps a runtime register, since physicalCol = rowStride is a runtime value there)

Rebased on top of linx (#79#81). Includes:

Main changes

  • 97 interfaces converted to per-dimension four-branch dispatch (~1436 B.DIM template lines audited, zero illegal forms)
  • PTO_MATMUL_HEADER: N/K now immediate-form (resolver is constexpr; the code's own comment admitted "compile-time exact even though passed through GPR"); M stays a register since cooperative group_M is genuinely runtime
  • THISTOGRAM fix: the macro's B.DATR %D2, paste produced unmatchable asm (missing space + PadValue); never compiled because no fixture covered it. Template now four-branch parameterized
  • TLOAD2/TLOAD4/TSTORE2 lb2 immediate-slot form fixed
  • Removed fa-56 legacy dead code: TMAX_T, TSUB_EXP_EXPAND_T, TMUL_ADD_ROWSUM_T, TADD_MUL_EXPAND_T, TMOV_DN2NZ_DYN, DEFINE_TMOV_LAYOUT variants (zero callers; the VPAR raw-opcode spelling does not assemble — superseded by region helpers)
  • Fixed pre-existing BLayout::ND2M16/32LayoutCvtEnum (also present in Docs/timg2col contract alignment #81's new code)

Verification

  • test_v058_engine_contract: 40/40 OK (assertions strengthened: no "ri" masquerade, lb2 immediate invariant, TMATMUL M/N/K forms)
  • New ValidShapePerDimSweep.cpp: compile-time sweep of ~65 interface instantiations × four combinations (elementwise, unary, row/col reduce, scalar variants, TCMP/THISTOGRAM/TLOAD_CUBE/TSTORE_CUBE); disassembly form matrix is symmetric (96 static + 96 dynamic per lb0/lb1, lb2 all immediate), zero illegal forms
  • Full compile gate: 63/74 fixtures pass; the 11 failures reproduce identically on pristine origin/linx (pre-existing issues: TLOAD "i"-constraint bug, static_assert limits in DynamicShape/TRowMax, Global template missing in ValidShapeImmediate, TImg2Col/TMatmulAllOptions pre-existing match errors)
  • B.DIM ordering audit: 100% DIM-before-IOT/IOS (canonical)
  • git diff --check clean

LinxISA Automation added 3 commits September 7, 2026 23:42
Split every lb0/lb1 B.DIM site into four if-constexpr branches on
ValidCol/ValidRow (SS/SD/DS/DD):
- static dim  -> B.DIM zero, %c[imm]  (compresses to C.B.DIMI)
- dynamic dim -> B.DIM %[reg], 0
lb2 always stays the immediate form (only TPREFETCH's dynamic-GM
fallback keeps a runtime register).

Also:
- make TMATMUL N/K immediate-form (M stays a register: group_M is
  runtime for cooperative forms)
- fix THISTOGRAM: missing space/PadValue in the B.DATR paste made the
  macro un-compilable; template now four-branch parameterized
- fix TLOAD2/TLOAD4/TSTORE2 lb2 immediate-slot form
- remove fa-56 legacy dead code: TMAX_T, TSUB_EXP_EXPAND_T,
  TMUL_ADD_ROWSUM_T, TADD_MUL_EXPAND_T, TMOV_DN2NZ_DYN and the
  DEFINE_TMOV_LAYOUT variants (no callers; VPAR raw-opcode spelling
  does not assemble)
- fix pre-existing BLayout::ND2M16/32 -> LayoutCvtEnum in TIMG2COL
- ValidShapePerDim.cpp: TADD/TMUL/TRECIP/TEXP across SS/SD/DS/DD
- ValidShapePerDimSweep.cpp: compile-time sweep of ~65 interface
  instantiations x four combinations (elementwise, unary, row/col
  reduce, scalar variants, TCMP/THISTOGRAM/TLOAD_CUBE/TSTORE_CUBE);
  disassembly form matrix is symmetric (96 static + 96 dynamic per
  lb0/lb1, lb2 all immediate) with zero illegal forms
- compile.all: register both fixtures
- test_v058_engine_contract.py: assert no "ri" masquerade, lb2
  immediate-form invariant (TPREFETCH dynamic-GM fallback exempted),
  TMATMUL M/N/K forms; update TCVT anchors for the removed
  DEFINE_TMOV_LAYOUT macro
@VV0003
VV0003 merged commit 67d47ab into linx Sep 7, 2026
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@VV0003

VV0003 commented Sep 7, 2026

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Sweep coverage extended — the first sweep only covered 48 of the 97 four-branch interfaces; a re-audit flagged the remaining 49. Added in 37935d0:

  • TPARTADD/MAX/MIN/MUL, TSEL, TFMA, TFILLPAD, TEXTRACT, TINSERT, TEXPANDS, TDEQUANT
  • TROWEXPAND* / TROWARGMAX/MIN, TCOLEXPAND* / TCOLARGMAX/MIN (broadcast shape contracts)
  • TGATHER / TSCATTER (offset-tile driven dispatch)
  • Shared TSTORE ×4 combinations

Now 101 four-combination instantiations, zero compile errors. Disassembly form matrix across the whole fixture:

label static (C.B.DIMI) dynamic (B.DIM reg,0)
lb0 170 162
lb1 170 162
lb2 320 0

Symmetric static/dynamic pairs on lb0/lb1, lb2 always immediate, zero illegal forms.

Note on Shared TSTORE: the sweep uses TMOV_L2S_INSERT inline (Shared values must never cross the C++ ABI); passing SharedTile as a noinline function argument triggers the known setRegClass assertion — verified reproducible on the unmodified baseline.

Not sweepable due to pre-existing blockers (identical on baseline): TLOAD2/TLOAD4 (B.DATR ND2NZ alias missing .normal), TIMG2COL/TMATMUL-options match errors, TLOAD plain-form "i"-constraint bug.

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