intel-max10

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BJaideep18 / FPGA-chess-DE10lite

Developed a fully functional chess game on an Intel MAX10 FPGA using System Verilog. The game runs on a VGA monitor at 640×480, accepts input via a matrix keypad, enforces all official chess rules in hardware, and renders the board and pieces procedurally at the pixel level all without a soft-core processor or external memory.

chess fpga systemverilog vga digital-design de10-lite hardware-design intel-max10

Updated Jun 28, 2026
SystemVerilog

avaamar / f1-reaction-timer-fpga

Star

F1 starting light reaction timer on Intel MAX10 FPGA. SystemVerilog FSM, LFSR random delay, hierarchical clock management. Imperial College London (Grade: A).

fsm fpga hardware systemverilog digital-design lfsr quartus imperial-college-london rtl-design intel-max10

Updated Aug 31, 2026
SystemVerilog

lruizleonardo1 / FPGA-SPWM-Sine-Wave-Inverter

Star

FPGA-based single-phase SPWM sine-wave inverter using an Intel MAX 10, VHDL, H-bridge power stage, step-up transformer, and experimental validation at 120 V RMS / 60 Hz.

fpga vhdl pwm power-electronics digital-design quartus spwm h-bridge intel-max10 sine-wave-inverter dc-ac-inverter

Updated Sep 9, 2026
VHDL

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